In recent years, the mobile device becomes more and more popular among the computer, the consumer, and the communication products. In particular, the mobile phone, the laptop, or the pad product is increasingly demanded and sold at a great percentage of the electrical devices around the world.
The major concern of those mobile phones is about the power consumption and the battery life thereof. The power management can improve the chip's power efficiency so as to prolong the battery life and the operating time.
Although the mobile phone is designed to have low power consumption, it still needs power to support a standby mode in order that it wakes up to receive a prepared call. Even if there is no voice communication, a power circuit of the mobile phone is still powered to allow a background communication called a “paging mode”. While the mobile phone is inactive, most circuits of the mobile phone except the power circuit are shut down for saving the power consumption.
While the mobile phone is in the standby mode, the power circuit being the analog portion of the mobile phone is still active to power the digital portion of the mobile phone. For example, the power circuit is a low drop-out (LDO) regulator. The LDO regulator is an essential part of a power management system that provides a constant supply voltage. The conventional LDO regulator, for stability requirements, requires a relatively large-capacity output capacitor in the single microfarad range. A large-capacity microfarad capacitor cannot be realized into a chip, and thus each LDO regulator needs an external pin for a board-mounted output capacitor.
While the LDO regulator is powered, a quiescent current flowing therein makes power consumption; and the mobile phone often includes lots of LDO regulators, so that the total power consumption is relatively large. The quiescent current is defined as the operation current of the amplifier of the LDO regulator. A large-capacity off-chip external capacitor is used for frequency compensation.
Please refer to FIG. 1, which shows an LDO regulator circuit 10 in the prior art. The regulator circuit 10 includes a first amplifier 101, a second amplifier 102, a first bias current source 103, a second bias current source 104, a first switch 105, a second switch 106, a main bandgap circuit 107, an inverter 109, a power p-type metal oxide semiconductor (PMOS) transistor MP1, a divider portion DIVR1, an external load capacitor CLOAD1, and an equivalent load RLOAD1, wherein the divider portion DIVR1 includes resistors R1 and R2, and the equivalent load RLOAD1 has a load current ILOAD1 flowing therethrough.
The LDO regulator circuit 10 includes an LDO power supply unit; and the basic structure of the LDO power supply unit includes the power PMOS transistor MP1, the first amplifier 101, the first bias current source 103, the external load capacitor CLOAD1, the divider portion DIVR1, and the main bandgap circuit 107. The output terminal EO1 of the first amplifier 101 is coupled to the gate G1 of the power PMOS transistor MP1; and the first bias current source 103 is coupled to the power PMOS transistor MP1. A system voltage VIN is supplied to the first amplifier 101, the second amplifier 102, and the source terminal S1 of the power PMOS transistor MP1. The main bandgap circuit 107 generates a reference voltage VBG1 to be provided to the negative input of the first amplifier 101 and the negative input of the second amplifier 102. The divider portion DIVR1 provide a feedback voltage VFB1 to the positive input of the first amplifier 101 and the positive input of the second amplifier 102.
For example, the first amplifier 101 is an error amplifier. When the magnitude of the feedback voltage VFB1 is less than that of the reference voltage VBG1, the first amplifier outputs a relatively low voltage level to turn on the power PMOS transistor MP1 for making a conduction between the source terminal S1 and the drain terminal D1 of the power PMOS transistor MP1. Thus the system voltage VIN can be supplied to the external load capacitor CLOAD1, the divider portion DIVR1, and the equivalent load RLOAD1. When the magnitude of the feedback voltage VFB1 is larger than that of the reference voltage VBG1, the first amplifier 101 outputs a relatively high voltage level to turn off the power PMOS transistor MP1 for reducing an output voltage VOUT1 at the drain terminal D1 which is also an output terminal of the LDO power supply unit. The output voltage VOUT1 has a waveform which is like a small sinusoid wave with a small swing. If the design of the LDO regulator circuit 10 is careless, the small wave will swing to be unlimited large increasingly, which results in an unstable power to be supplied to the load capacitor CLOAD1 and the equivalent load RLOAD1.
The inverter 109 coupled to the first switch 105 and the second switch 106 receives a control signal STBEN1 to turn on one of the first and the second switches 105 and 106 for enabling one of an active mode and a standby mode. When the first switch 105 is turned on and the second switch 106 is turned off, the LDO regulator circuit 10 enters the active mode and only the first bias current source 103 provides an active current Iq_act1 in the active mode. On the contrary, when the second switch 106 is turned on and the first switch 105 is turned off, the LDO regulator circuit 10 enters the standby mode and only the second bias current source 104 provides a standby current Iq_stb1 in the standby mode.
The second amplifier 102 may be designed to consume a less power than the first amplifier 101 consumes, and the second bias current source 104 can also be designed to provide less current than the first bias current source 103 provides. Thus, when a demand of the load current ILOAD1 is light, the control signal STBEN1 can switch the LDO regulator circuit 10 into the standby mode for saving power; and when the demand of the load current ILOAD1 is heavy, the control signal STBEN1 can switch the LDO regulator circuit 10 into the active mode for providing enough load current ILOAD1. The load current ILOAD1 is typically ranged from 10 μA to 100 mA according to the demand of the load current ILOAD1, which can be light or heavy. However, the disadvantage is that the larger standby current Iq_stb1 will result in the power consumption even in the standby mode with very light current load.
The LDO regulator circuit 10 can save power owing to its lowered quiescent current. For example, the consumed current of the LDO regulator circuit 10 is reduced from the first bias current Iq_act1 in the active mode to the second bias current Iq_stb1 in the standby mode. However, it cannot be guaranteed that the LDO regulator circuit 10 can provide a stable power. In addition, the second amplifier 102 still occupies a large chip area, which can be eliminated.
Furthermore, it is also very important that the output voltage VOUT1 provided by the LDO regulator circuit 10 can be stable and can be immune to the noise whether the LDO regulator circuit 10 is in the active mode or in the standby mode, and the quiescent current can still be reduced to minimum. Saving the chip area and saving the power consumption is also expected. Accordingly, there is a need for a method and an apparatus to reduce the power consumption, simultaneously keep the output voltage VOUT1 in a relatively stable state, and have an economical chip area.